Conventional semiconductor packaging techniques involve mounting semiconductor dice onto device carriers, such as lead frames or laminated substrates, during the packaging process. Although advances in packaging techniques have reduced the form factors of such device carriers such that manufactured packages have outlines that are almost similar to the outlines of the semiconductor dice being packaged (often referred to as “chip-scale packages”), the need to mount the semiconductor die onto a device carrier before packaging it introduces obstacles as to how far the size of the final package is reducible. Other disadvantages include a mismatch between the physical properties of the semiconductor die and the device carrier, giving rise to a higher risk of failure in the assembled packages.
In order to overcome the limitations of conventional semiconductor packaging techniques, it would be beneficial to avoid the need for the semiconductor die to be mounted onto a device carrier during packaging. Thus, the semiconductor dice are packaged while they are still part of the wafer. Such wafer-level packages would offer, amongst other things, the benefits of small size and low inductance.